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| 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH AND SRAM COMBO MEMORY FEATURES * Flexible dual-bank architecture * Support for true concurrent operations with no latency: Read bank b during program bank a and vice versa Read bank b during erase bank a and vice versa * Organization: 2,048K x 16 (Flash) 128K x 16 (SRAM) * Basic configuration: Flash Bank a (4Mb Flash for data storage) - Eight 4K-word parameter blocks - Seven 32K-word blocks Bank b (28Mb Flash for program storage) - Fifty-six 32K-word main blocks SRAM 2Mb SRAM for data storage - 128K-words * F_VCC, VCCQ, F_VPP, S_VCC voltages1 1.65V (MIN)/1.95V (MAX) F_VCC read voltage or 1.80V (MIN)/2.20V (MAX) F_VCC read voltage 1.65V (MIN)/1.95V (MAX) S_VCC read voltage or 1.80V (MIN)/2.20V (MAX) S_VCC read voltage 1.65V (MIN)/1.95V (MAX) VCCQ or 1.80V (MIN)/2.20V (MAX) VCCQ 1.80V (TYP) F_VPP (in-system PROGRAM/ERASE) 0.0V (MIN)/2.20V (MAX) F_VPP (in-system PROGRAM/ERASE) 2 12V 5% (HV) F_VPP (production programming compatibility) * Asynchronous access time1 Flash access time: 100ns or 110ns @ 1.65V F_VCC SRAM access time: 100ns @ 1.65V S_VCC * Page Mode read access1 Interpage read access: 100ns/110ns @ 1.65V F_VCC Intrapage read access: 35ns/45ns @ 1.65V F_VCC * Low power consumption * Enhanced suspend options ERASE-SUSPEND-to-READ within same bank PROGRAM-SUSPEND-to-READ within same bank ERASE-SUSPEND-to-PROGRAM within same bank * Read/Write SRAM during program/erase of Flash * Dual 64-bit chip protection registers for security purposes * PROGRAM/ERASE cycles 100,000 WRITE/ERASE cycles per block MT28C3212P2FL MT28C3212P2NFL Low Voltage, Extended Temperature BALL ASSIGNMENT 66-Ball FBGA (Top View) 1 A B C D E F G H NC NC NC 2 NC 3 A20 4 A11 5 A15 6 A14 7 A13 8 A12 9 F_VSS 10 VccQ 11 NC 12 NC A16 A8 A10 A9 DQ15 S_WE# DQ14 DQ7 F_WE# NC DQ13 DQ6 DQ4 DQ5 S_VSS F_RP# DQ12 S_CE2 S_VCC F_VCC F_WP# F_VPP A19 DQ11 DQ10 DQ2 DQ3 S_LB# S_UB# S_OE# DQ9 DQ8 DQ0 DQ1 A18 A17 A7 A6 A3 A2 A1 S_CE1# F_VCC A5 A4 A0 F_CE# F_VSS F_OE# NC NC NC Top View (Ball Down) * Cross-compatible command set support Extended command set Common Flash interface (CFI) compliant NOTE: 1. These specifications are guaranteed for operation within either one of two voltage ranges, 1.65V-1.95V or 1.80V-2.20V. Use only one of the two voltage ranges for PROGRAM and ERASE operations. 2. MT28C3212P2NFL only. OPTIONS MARKING * Timing 100ns -10 110ns -11 * Boot Block Top T Bottom B * VPP1 Range 0.9V-2.2V None 0.0V-2.2V N * Operating Temperature Range Commercial Temperature (0oC to +70oC) None Extended Temperature (-40oC to +85oC) ET * Package 66-ball FBGA (8 x 8 grid) FL Part Number Example: MT28C3212P2FL-10 TET 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 1 (c)2002, Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY GENERAL DESCRIPTION The MT28C3212P2FL and MT28C3212P2NFL combination Flash and SRAM memory devices provide a compact, low-power solution for systems where PCB real estate is at a premium. The dual-bank Flash is a high-performance, high-density, nonvolatile memory device with a revolutionary architecture that can significantly improve system performance. This new architecture features: * A two-memory-bank configuration supporting dual-bank burst operation; * A high-performance bus interface providing a fast page data transfer; and * A conventional asynchronous bus interface. The device also provides soft protection for blocks by configuring soft protection registers with dedicated command sequences. For security purposes, dual 64bit chip protection registers are provided. The embedded WORD WRITE and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). The WSM simplifies these operations and relieves the system processor of secondary tasks. An on-chip status register, one for each bank, can be used to monitor the WSM status to determine the progress of a PROGRAM/ERASE command. The erase/program suspend functionality allows compatibility with existing EEPROM emulation software packages. The device takes advantage of a dedicated power source for the Flash device (F_VCC) and a dedicated power source for the SRAM device (S_VCC), both at 1.65V-1.95V or 1.80V-2.20V for optimized power consumption and improved noise immunity. The MT28C3212P2FL and MT28C3212P2NFL devices support two VPP voltage ranges, VPP1 and VPP2. VPP1 is an incircuit voltage of 0.9V-2.2V (MT28C3212P2FL) or 0.0V- 2.2V (MT28C3212P2NFL). VPP2 is the production compatibility voltage of 12V 5%. The 12V 5% VPP2 is supported for a maximum of 100 cycles and 10 cumulative hours. See Table 1. The MT28C3212P2FL and MT28C3212P2NFL devices contain an asynchronous 2Mb SRAM organized as 128K-words by 16 bits. These devices are fabricated using an advanced CMOS process and high-speed/ ultra-low-power circuit technology. The MT28C3212P2FL and MT28C3212P2NFL devices are packaged in a 66-ball FBGA package with 0.80mm pitch. DEVICE MARKING Due to the size of the package, Micron's standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross referenced to Micron part numbers in Table 2. Table 1 VPP Voltage Ranges DEVICE MT28C3212P2FL MT28C3212P2NFL VOLTAGE RANGE VPP1 VPP2 0.9V-2.2V 11.4V-12.6V 0.0V-2.2V 11.4V-12.6V Table 2 Cross Reference for Abbreviated Device Marks PART NUMBER MT28C3212P2FL-10 BET MT28C3212P2FL-10 TET MT28C3212P2FL-11 BET MT28C3212P2FL-11 TET MT28C3212P2NFL-11 TET PRODUCT MARKING FW443 FW442 FW444 FW433 FW445 SAMPLE MARKING FX443 FX442 FX444 FX433 FX445 MECHANICAL SAMPLE MARKING FY443 FY442 FY444 FY433 FY445 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY PART NUMBERING INFORMATION Micron's low-power devices are available with several different combinations of features (see Figure 1). Valid combinations of features and their corresponding part numbers are listed in Table 3. Figure 1 Part Number Chart MT 28C 321 2 P 2 N FL-11 T ET Micron Technology Flash Family 28C = Dual-Supply Flash/SRAM Combo Operating Temperature Range None = Commercial (0C to +70C) ET = Extended (-40C to +85C) Boot Block Starting Address B = Bottom boot T = Top boot Density/Organization/Banks 321 = 32Mb (2,048K x 16) bank a = 1/8; bank b = 7/8 Access Time -10 = 100ns -11 = 110ns SRAM Density 2 = 2Mb SRAM (128K x 16) Package Code Read Mode Operation P = Asynchronous/Page Read FL = 66-ball FBGA (8 x 8 grid) VPP1 Range Operating Voltage Range 2 = 1.65V-1.95V or 1.80V-2.20V None = 0.9V-2.2V N = 0.0V-2.2V Table 3 Valid Part Number Combinations VPP1 RANGE 0.9V-2.2V 0.9V-2.2V 0.9V-2.2V 0.9V-2.2V 0.0V-2.2V ACCESS TIME (ns) 100 100 110 110 110 BOOT BLOCK STARTING ADDRESS Bottom Top Bottom Top Top OPERATING TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC PART NUMBER MT28C3212P2FL-10 BET MT28C3212P2FL-10 TET MT28C3212P2FL-11 BET MT28C3212P2FL-11 TET MT28C3212P2NFL-11 TET 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY BLOCK DIAGRAM F_WE# F_OE# F_CE# F_RP# A17-A20 F_VCC FLASH F_VPP Bank a F_WP# F_VSS 2,048K x 16 Bank b VCCQ DQ0-DQ15 SRAM 128K x 16 S_VCC A0-A16 S_CE1# S_CE2 S_OE# S_WE# S_VSS S_UB# S_LB# FLASH FUNCTIONAL BLOCK DIAGRAM PR Lock PR Lock Query Query/OTP OTP DQ0-DQ15 X DEC Data Input Buffer Data Register F_RST# F_CE# F_WE# F_OE# Program/ Erase Pump Voltage Generators Output Multiplexer DQ0-DQ15 Y/Z DEC Bank 1 Blocks Y/Z Gating/Sensing Manufacturer's ID Device ID Block Lock RCR ID Reg. CSM Status Reg. WSM I/O Logic Output Buffer A0-A20 Address Input Buffer Address CNT/WSM Address Multiplexer Y/Z DEC X DEC Y/Z Gating/Sensing Bank 2 Blocks Address Latch 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY BALL DESCRIPTIONS 66-BALL FBGA NUMBERS A3, A4, A5, A6, A7, A8, B3, B4, B5, B6, E5, G3, G4, G5, G6, G7, G8, G9, H4, H5, H6 H7 H9 C3 D4 SYMBOL A0-A20 TYPE Input DESCRIPTION Address Inputs: Inputs for the addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. Flash: A0-A20; SRAM: A0-A16. F_CE# F_OE# F_WE# F_RP# Input Input Input Input Flash Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Flash Output Enable: Enables Flash output buffers when LOW. When F_OE# is HIGH, the output buffers are disabled. Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle. F_WE# is active LOW. Reset. When F_RP# is a logic LOW, the device is in reset, which drives the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH, the device is in standard operation. When F_RP# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode. Flash Write Protect. Controls the lock down function of the flexible locking feature. SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level deselects the SRAM and reduces the power consumption to standby levels. SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level deselects the SRAM and reduces the power consumption to standby levels. SRAM Output Enable: Enables SRAM output buffers when LOW. When S_OE# is HIGH, the output buffers are disabled. SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle. S_WE# is active LOW. SRAM Lower Byte: When LOW, it selects the SRAM address lower byte (DQ0-DQ7). SRAM Upper Byte: When LOW, it selects the SRAM address upper byte (DQ8-DQ15). Data Inputs/Outputs: Input array data on the second CE# and WE# cycle during PROGRAM command. Input commands to the command user interface when CE# and WE# are active. Output data when CE# and OE# are active. E3 G10 F_WP# S_CE1# Input Input D8 S_CE2 Input F5 B8 F3 F4 S_OE# S_WE# S_LB# S_UB# Input Input Input Input B7, B9, B10, DQ0-DQ15 Input/ C7, C8, C9, Output C10, D7, E6, E8, E9, E10, F7, F8, F9, F10 (continued on next page) 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY BALL DESCRIPTIONS (continued) 66-BALL FBGA NUMBERS E4 SYMBOL F_VPP TYPE Input/ Supply DESCRIPTION Flash Program/Erase Power Supply: [0.9V-2.2V or 11.4V-12.6V]. Operates as input at logic levels to control complete device protection. Provides backward compatibility for factory programming when driven to 11.4V-12.6V. A lower F_VPP voltage range (0.0V-2.2V) is available on the MT28C3212P2NFL device. Flash Power Supply: [1.65V-1.95V or 1.80V-2.20V]. Supplies power for device operation. Flash Specific Ground: Do not float any ground pin. SRAM Power Supply: [1.65V-1.95V or 1.80V-2.20V]. Supplies power for device operation. SRAM Specific Ground: Do not float any ground pin. I/O Power Supply: [1.65-1.95V or 1.80V-2.20V]. This input should be tied directly to VCC. No Connect: Lead is not internally connected; it may be driven or floated. D10, H3 A9, H8 D9 D3 A10 A1, A2, A11, A12, C4, H1, H2, H10, H11, H12 F_VCC F_VSS S_VCC S_VSS VCCQ NC Supply Supply Supply Supply Supply - 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY TRUTH TABLE - FLASH MODES Read Write Standby Output Disable Reset FLASH SIGNALS SRAM SIGNALS F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB# H H H H L L L H L X L H X H X H L X H X SRAM must be High-Z MEMORY OUPUT MEMORY DQ0-DQ15 BUS CONTROL Flash Flash Other Other Other DOUT DIN High-Z High-Z High-Z NOTES 1, 2, 3 1 4 4, 5 4, 6 SRAM any mode allowable TRUTH TABLE - SRAM MODES Read DQ0-DQ15 DQ0-DQ7 DQ8-DQ15 Write DQ0-DQ15 DQ0-DQ7 DQ8-DQ15 Standby Output Disable NOTE: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. FLASH SIGNALS SRAM SIGNALS F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB# MEMORY OUPUT MEMORY DQ0-DQ15 BUS CONTROL SRAM SRAM SRAM SRAM SRAM SRAM Other Other Other DOUT DOUT LB DOUT UB DIN DIN LB DIN UB High-Z High-Z High-Z NOTES Flash must be High-Z L L L L L L H X L H H H H H H X L H L L L H H H X X X H H H L L L X X X L H L L H L X X X L L H L L H X X X 1, 3 7 8 1, 3 9 10 4 4 4 Flash any mode allowable Two devices may not drive the memory bus at the same time. Allowable flash read modes include read array, read query, read configuration, and read status. Outputs are dependent on a separate device controlling bus outputs. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to control the bus outputs at a time. Data output on lower byte only; upper byte High-Z. Data output on upper byte only; lower byte High-Z. Data input on lower byte only. Data input on upper byte only. 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH ARCHITECTURE AND MEMORY ORGANIZATION The Flash memory device contains two separate memory banks (bank a and bank b) for simultaneous READ and WRITE operations. Bank a is 2Mb deep and contains 8 x 4K-word parameter blocks and seven 32Kword blocks. Bank b is 28Mb deep, is equally sectored, and contains fifty-six 32K-word blocks. Figures 2 and 3 show the top and bottom memory organizations. 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Address Range (x16) 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh Figure 2 Bottom Boot Block Device Block 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Bank b = 28Mb Block Size (K-bytes/K-words) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (x16) 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D800h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-097FFFh 090000h-097FFFh 088000h-087FFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-067FFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh Block 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank a = 4Mb Block Size (K-bytes/K-words) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Address Range (x16) 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 000000h-007FFFh Figure 3 Top Boot Block Device Block 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 Bank a = 4Mb Block Size (K-bytes/K-words) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (x16) 1FF000h-1FFFFFh 1FE000h-1FEFFFh 1FD000h-1FDFFFh 1FC000h-1FCFFFh 1FB000h-1FBFFFh 1FA000h-1FAFFFh 1F9000h-1F9FFFh 1F8000h-1F8FFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh Block 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank b = 28Mb Block Size (K-bytes/K-words) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH MEMORY OPERATING MODES COMMAND STATE MACHINE Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external microprocessors and the internal write state machine (WSM). The available commands are listed in Table 4, their definitions are given in Table 5 and their descriptions in Table 6. Program and erase algorithms are automated by the on-chip WSM. Table 7 shows the CSM transition states. Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate algorithm, which generates the necessary timing signals to control the device internally. A command is valid only if the exact sequence of WRITEs is completed. After the WSM completes its task, the write state machine status (WSMS) bit (SR7) (see Table 9) is set to a logic HIGH level (VIH), allowing the CSM to respond to the full command set again. OPERATIONS Device operations are selected by entering a standard JEDEC 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/O pins DQ0-DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control pins F_CE# and F_WE# must be at a logic LOW level (VIL), and F_OE# and F_RP# must be at logic HIGH (VIH). The second operation, when needed, can be a WRITE or a READ depending upon the command. During a READ operation, control pins F_CE# and F_OE# must be at a logic LOW level (VIL), and F_WE# and F_RP# must be at logic HIGH (VIH). Table 8 illustrates the bus operations for all the modes: write, read, reset, standby, and output disable. When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a command code be entered into the CSM. For each one of the two flash memory partitions, an on-chip status register is available. These two registers allow the monitoring of the progress of various operations that can take place on a memory bank. One of the two status registers is interrogated by entering a READ STATUS REGISTER command onto the CSM (cycle 1), specifying an address within the memory partition boundary, and reading the register data on I/O pins DQ0-DQ7 (cycle 2). Status register bits SR0-SR7 correspond to DQ0-DQ7 (see Table 9). COMMAND DEFINITION Once a specific command code has been entered, the WSM executes an internal algorithm, generating the necessary timing signals to program, erase, and verify data. See Table 5 for the CSM command definitions and data for each of the bus cycles. STATUS REGISTER The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored by toggling F_OE# and F_CE# and reading the resulting status code on I/O pins DQ0-DQ7. The high-order I/Os (DQ8-DQ15) are set to 00h internally, so only the Table 4 Command State Machine Codes For Device Mode Selection COMMAND DQ0-DQ7 10h/40h 20h 50h 60h 70h 90h 98h B0h C0h D0h FFh 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 CODE ON DEVICE MODE Program setup/alternate program setup Block erase setup Clear status register Protection configuration setup Read status register Read protection configuration register Read query Program/erase suspend Protection register program/lock Program/erase resume - erase confirm Read array 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY low-order I/O pins (DQ0-DQ7) need to be interpreted. Address lines select the status register pertinent to the selected memory partition. Register data is updated and latched on the rising edge of F_OE# or F_CE#, whichever occurs first. The latest falling edge of either of these two signals updates the latch within a given READ cycle. Latching the data prevents errors from occurring if the register input changes during a status register read. The status register provides the internal state of the WSM to the external microprocessor. During periods when the WSM is active, the status register can be polled to determine the WSM status. Table 9 defines the status register bits. After monitoring the status register during a PROGRAM/ERASE operation, the data appearing on DQ0-DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM. COMMAND STATE MACHINE OPERATIONS The CSM decodes instructions for the commands listed in Table 4. The 8-bit command code is input to the device on DQ0-DQ7 (see Table 5 for command definitions). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested. During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PROGRAM SUSPEND command only. During an ERASE cycle, the CSM responds to an ERASE SUSPEND command only. When the WSM has completed its task, the WSMS bit (SR7) is set to a logic HIGH level and the CSM responds to the full command set. The CSM stays in the current command state until the microprocessor issues another command. The WSM successfully initiates an ERASE or PROGRAM operation only when VPP is within its correct voltage range. Table 5 Command Definitions FIRST BUS CYCLE COMMAND READ ARRAY READ PROTECTION CONFIGURATION REGISTER READ STATUS REGISTER CLEAR STATUS REGISTER READ QUERY BLOCK ERASE SETUP PROGRAM SETUP/ALTERNATE PROGRAM SETUP PROGRAM/ERASE SUSPEND PROGRAM/ERASE RESUME - ERASE CONFIRM LOCK BLOCK UNLOCK BLOCK LOCK DOWN BLOCK PROTECTION REGISTER PROGRAM PROTECTION REGISTER LOCK NOTE: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. OPERATION ADDRESS WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WA IA BA BA QA BA WA BA BA BA BA BA PA LPA DATA FFh 90h 70h 50h 98h 20h 40h/10h B0h D0h 60h 60h 60h C0h C0h WRITE WRITE WRITE WRITE WRITE BA BA BA PA LPA 01h D0h 2Fh PD FFFDh READ WRITE WRITE QA BA WA QD D0h WD READ READ IA BA ID SRD SECOND BUS CYCLE OPERATION ADDRESS DATA WA: Word address of memory location to be written, or read IA: Identification code address BA: Address within the block ID: Identification code data SRD: Data read from the status register QA: Query code address QD: Query code data WD: Data to be written at the location WA PA: Protection register address LPA: Lock protection register address PD: Protection register data 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Table 6 Command Descriptions CODE DEVICE MODE 10h 20h Alt. Program Setup Erase Setup BUS CYCLE First First DESCRIPTION Operates the same as a PROGRAM SETUP command. Prepares the CSM for an ERASE CONFIRM command. If the next command is not ERASE CONFIRM, the CSM sets both SR4 and SR5 of the status register to a "1," places the device into read status register mode, and waits for another command. A two-cycle command: The first cycle prepares for a PROGRAM operation, the second cycle latches addresses and data and initiates the WSM to execute the program algorithm. The Flash outputs status register data on the falling edge of F_OE# or F_CE#, whichever occurs first. The WSM can set the program status (SR4), and erase status (SR5) bits in the status register to "1," but it cannot clear them to "0." Issuing this command clears those bits to "0." Prepares the CSM for changes to the block locking status. If the next command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK DOWN, then the CSM sets both the program and erase status register bits to indicate a command sequence error. Places the device into read status register mode. Reading the device outputs the contents of the status register, regardless of the address presented to the device. The device automatically enters this mode after a PROGRAM or ERASE operation has been initiated. Puts the device into the read protection configuration mode so that reading the device outputs the manufacturer/device codes or block lock status. Puts the device into the read query mode so that reading the device outputs common Flash interface information. Suspends the currently executing PROGRAM/ERASE operation. The status register indicates when the operation has been successfully suspended by setting either the program suspend (SR2) or erase suspend (SR6) and the WSMS bit (SR7) to a "1" (ready). The WSM continues to idle in the suspend state, regardless of the state of all input control pins except F_RP#, which immediately shuts down the WSM and the remainder of the chip if F_RP# is driven to VIL. Writes a specific code into the device protection register. Locks the device protection register; data can no longer be changed. 40h Program Setup First 50h Clear Status Register Protection Configuration Setup Read Status Register First 60h First 70h First 90h Read Protection Configuration Read Query Program Suspend Erase Suspend First 98h B0h First First First C0h Program Device Protection Register Lock Device Protection register First First (continued on the next page) 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Table 6 Command Descriptions (continued) CODE DEVICE MODE D0h Erase Confirm BUS CYCLE First DESCRIPTION If the previous command was an ERASE SETUP command, then the CSM closes the address and data latches, and it begins erasing the block indicated on the address pins. During programming/erase, the device responds only to the READ STATUS REGISTER, PROGRAM SUSPEND, or ERASE SUSPEND commands and outputs status register data on the falling edge of F_OE# or F_CE#, whichever occurs last. If a PROGRAM or ERASE operation was previously suspended, this command resumes the operation. During the array mode, array data is output on the data bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM latches the address and locks the block indicated on the address bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM latches the address and locks down the block indicated on the address bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM latches the address and unlocks the block indicated on the address bus. If the block had been previously set to lock down, this operation has no effect. Unassigned command that should not be used. Program/Erase Resume FFh 01h Read Array Lock Block First First Second 2Fh Lock Down Second D0h Unlock Block Second 00h Invalid/Reserved 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY CLEAR STATUS REGISTER The internal circuitry can set, but not clear, the block lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear these status bits and synchronize to the internal operations. When the status bits are cleared, the device returns to the read array mode. and the identification code address on the address lines. Control pins F_CE# and F_OE# must be at a logic LOW level (VIL), and F_WE# and F_RP# must be at a logic HIGH level (VIH) to read data from the protection configuration register. Data is available on DQ0-DQ15. After data is read from the protection configuration register, the READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. See Table 11 for further details. READ QUERY The read query mode outputs common Flash interface (CFI) data when the device is read (see Table 15). Two bus cycles are required for this operation. It is possible to access the query by writing the read query command code 98h on DQ0-DQ7. Control pins F_CE# and F_OE# must be at a logic LOW level (VIL), and F_WE# and F_RP# must be at a logic HIGH level (VIH) to read data from the query. The CFI data structure contains information such as block size, density, command set, and electrical specifications. To return to read array mode, write the read array command code FFh on DQ0- DQ7. READ STATUS REGISTER The status register is read by entering the command code 70h on DQ0-DQ7. Two bus cycles are required for this operation: one to enter the command code and a second to read the status register. In a READ cycle, the address is latched and register data is updated on the falling edge of F_OE# or F_CE#, whichever occurs last. READ OPERATIONS The following READ operations are available: READ ARRAY, READ PROTECTION CONFIGURATION REGISTER, READ QUERY and READ STATUS REGISTER. READ ARRAY The array is read by entering the command code FFh on DQ0-DQ7. Control pins F_CE# and F_OE# must be at a logic LOW level (VIL), and F_WE# and F_RP# must be at a logic HIGH level (VIH) to read data from the array. Data is available on DQ0-DQ15. Any valid address within any of the blocks selects that address and allows data to be read from that address. Upon initial power-up, the device defaults to the read array mode. READ CHIP PROTECTION IDENTIFICATION DATA The chip identification mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. Two bus cycles are required for this operation: the chip identification data is read by entering the command code 90h on DQ0-DQ7 to the bank containing address 00h 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Present state of the other partition 1 Read array Read array 2 Read array OTP setup Lock Read query Read ID Read array Read status Read array Read array Read array Read array 5 6 Read array Read array 7 Read array OTP setup Lock Read query Read ID Read array Read status Read array Read array Read array Read array Read 11 Read array Read array 12 Read array OT P setup Lock Read query Read ID Read array Read status Read array Read array Read array Read array 15 16 Read array Read array 17 Read array OT P setup Lock Read query Read ID Read array Read status Read array Read array Read array Read array Protection register busy Protection register busy 1 0 Status Status Setup Busy P r o t e c t i o n r e g i s t e r 20 21 22 23 24 25 Erase setup Program Read setup array 1 Status Status 18 19 Busy Idle Erase suspend Prog. suspend Idle Idle Setup Busy Idle Erase suspend Prog. suspend Erase setup Program Read setup array 1 ID Device ID 13 14 Busy Idle Erase suspend Prog. suspend Setup 10 Erase setup Program Read setup array 1 CFI Query 8 9 Busy Idle Erase suspend Prog. suspend Setup Erase setup Program Read setup array 1 Array Array 3 4 Busy Idle Erase suspend Prog. suspend Setup Setup 26 27 Table 7 Command State Machine Transition Table Command input to the present partition (and next state of the present partition) 2Fh 01h Lock Lock down confirm confirm C0h 60h OTP Lock/Unlock setup /Lock down 98h Read query 90h Read device ID 50h 70h Clear Read status status register B0h Program /Erase suspend D0h BE confirm, P/E resume, ULB confirm 20h 10h/40h FFh Erase Program Read setup setup array Present state of the present partition SR7 Data when read State Mode Read array Lock Read query Read ID Read array Read status Read array 1 Status Done Read array OTP setup Lock Read query Read ID Read array Read status Read array Erase setup Program Read setup array 1 Status Done Read array Read array Read array (continued on next page) 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Present state of the other partition 28 29 Read array OTP setup Read array 30 Read array Read query Read array Read status Read array Read array Read array Read array Lock 33 34 Read array O TP setup Read array 35 Read array Read query Read array Read status Read array Read array Read array Read array Program Busy Program Busy PS read Program busy 1 0 Status Status Setup Busy 38 39 40 41 Read array Read array Program Read array OTP setup Lock Read query Read ID Read array Read status Read array Read array Read array Read array 45 46 Program suspend read array Lock Program suspend read query Program suspend read ID Program suspend read array Program Program suspend suspend Program suspend read Program busy read read array status array 1 Status Read status Program suspend 47 48 Erase setup Program Read setup array 1 Status Done 42 43 44 Busy Idle Erase suspend Prog. suspend Setup Idle Erase suspend Erase setup Program Read setup array Lock/ Unlock 36 37 Busy Idle Erase suspend Prog. suspend Any state Idle Setup Erase setup Program Read setup array 31 32 Busy Idle Erase suspend Prog. suspend Setup Any state Setup Table 7 Command State Machine Transition Table (continued) Command input to the present partition (and next state of the present partition) 2Fh 01h Lock Lock down confirm confirm C0H 60h OTP Lock/Unlock setup /Lock down 98h Read query 90h 50h Read Clear device ID status register 70h Read status B0h Program /Erase suspend D0h BE confirm, P/E resume, ULB confirm 20h 10h/40h FFh Erase Program Read setup setup array Present state of the present partition SR7 Data when read State Mode LB/ULB Lock L LB/ULB Lock 1 Status Setup Lock Read ID 1 Status Error Lock Read ID 1 Status (continued on next page) 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Present state of the other partition 49 1 Array Read array 50 51 52 Program suspend read array Lock Program suspend read query Program suspend read ID Program suspend read array Program Program suspend suspend Program suspend read Program busy read read array status array 1 Table 7 Command State Machine Transition Table (continued) Command input to the present partition (and next state of the present partition) 2Fh 01h Lock Lock down confirm confirm C0h 60h OTP Lock/Unlock setup /Lock down 98h Read query 90h 50h Read Clear device ID status register 70h Read status B0h Program /Erase suspend D0h BE confirm, P/E resume, ULB confirm 20h 10h/40h FFh Erase Program Read setup setup array Present state of the present partition Data when read SR7 State Mode Program suspend read array Lock Program suspend read query Program suspend read ID Program suspend read array Program Program suspend suspend Program suspend read Program busy read read array status array Setup Idle Erase suspend Setup Idle Erase suspend Setup Idle Erase suspend Idle Setup Busy Idle Erase suspend Prog. suspend Setup Busy Idle Erase suspend Prog. suspend Idle ID Read ID Program suspend 53 54 55 Program suspend read array Lock Program suspend read query Program suspend read ID Program suspend read array Program Program suspend suspend Program suspend read Program busy read read array status array Erase error 1 CFI Read Query 56 57 LB/ULB Erase error Erase busy Erase error 1 Status Setup 58 59 Read array OTP setup Read array 60 Erase setup Program Read setup array Read array Lock Read query Read ID Read array Read status Read array Read array 1 Status Error 61 62 63 Erase 64 Read array Read array Read array OTP setup Read array 65 Read array Lock Read query Read ID Read array Read status Read array Read array Erase Program Read setup array 1 Status Done 66 67 68 Read array Read array Block erase busy ES read status Erase busy 0 Status Busy 69 (continued on next page) 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Present state of the other partition 70 71 ES read array 1 Table 7 Command State Machine Transition Table Command input to the present partition (and next state of the present partition) 2Fh 01h Lock Lock down confirm confirm C0h 60h OTP Lock/Unlock setup /Lock down 98h Read query 90h 50h Read Clear device ID status register 70h Read status B0h Program /Erase suspend ES read array Erase suspend read query Erase suspend read ID Erase suspend read array Erase suspend read status D0h BE confirm, P/E resume, ULB confirm Erase busy 20h 10h/40h FFh Erase Program Read setup setup array Present state of the present partition Data when read SR7 State Mode Erase suspend read array Setup Busy Idle Prog. suspend Setup Busy Idle Prog. suspend Setup Busy Erase suspend read array ES read array Erase busy ES read array Prog. setup Status Read status Erase suspend read array Lock 72 Erase suspend read array ES read array Erase suspend read query Erase suspend read ID Erase suspend read array Erase suspend read status Erase busy Erase suspend read array 73 74 75 ES read array 1 Array Read array 76 Erase suspend read array ES read array Erase busy ES read array Prog. setup Erase suspend read array Lock Erase suspend read array ES read array Erase suspend read query Erase suspend read ID E rase suspend read array Erase suspend read status Erase busy Erase suspend read array Erase suspend 77 78 79 ES read array 1 Erase suspend read array ES read array ES read array Prog. setup ID Read ID Erase suspend read array Lock Erase busy 80 Idle Prog. suspend Setup Busy Erase suspend read array ES read array Erase suspend read query Erase suspend read ID Erase suspend read array Erase suspend read status Erase busy Erase suspend read array 81 82 83 ES read array 1 CFI Read query Erase suspend read array ES read array ES read array Prog. setup Erase suspend read array Lock Erase busy 84 Idle Prog. suspend Erase suspend read array 85 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY PROGRAMMING OPERATIONS There are two CSM commands for programming: PROGRAM SETUP and ALTERNATE PROGRAM SETUP (see Table 4). After the desired command code is entered (10h or 40h command code on DQ0-DQ7), the WSM takes over and correctly sequences the device to complete the PROGRAM operation. The WRITE operation may be monitored through the status register (see the Status Register section). During this time, the CSM only responds to a PROGRAM SUSPEND command until the PROGRAM operation has been completed, after which time all commands to the CSM become valid again. The PROGRAM operation can be suspended by issuing a PROGRAM SUSPEND command (B0h). Once the WSM reaches the suspend state, it allows the CSM to respond only to READ ARRAY, READ STATUS REGISTER, READ PROTECTION CONFIGURATION, READ QUERY, PROGRAM SETUP, or PROGRAM RESUME. During the PROGRAM SUSPEND operation, array data should be read from an address other than the one being programmed. To resume the PROGRAM operation, a PROGRAM RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 4 for programming operation and Figure 5 for program suspend and program resume). Taking F_RP# to VIL during programming aborts the PROGRAM operation. plished only by blocks; data at single address locations within the array cannot be erased individually. The block to be erased is selected by using any valid address within that block. Block erasure is initiated by a command sequence to the CSM: BLOCK ERASE setup (20h) followed by BLOCK ERASE CONFIRM (D0h) (see Table 5). A two-command erase sequence protects against accidental erasure of memory contents. When the BLOCK ERASE CONFIRM command is complete, the WSM automatically executes a sequence of events to complete the block erasure. During this sequence, the block is programmed with logic 0s, data is verified, all bits in the block are erased, and finally verification is performed to ensure that all bits are correctly erased. Monitoring of the ERASE operation is possible through the status register (see the Status Register section). During the execution of an ERASE operation, the ERASE SUSPEND command (B0h) can be entered to direct the WSM to suspend the ERASE operation. Once the WSM has reached the suspend state, it allows the CSM to respond only to the READ ARRAY, READ STATUS REGISTER, READ QUERY, READ CHIP PROTECTION CONFIGURATION, PROGRAM SETUP, PROGRAM RESUME, ERASE RESUME and LOCK SETUP (see the Block Locking section). During the ERASE SUSPEND operation, array data must be read from a block other than the one being erased. To resume the ERASE operation, an ERASE RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 7). It is also possible that an ERASE in any bank can be suspended and a WRITE to another block in the same bank can be initiated. After the completion of a WRITE, an ERASE can be resumed by writing an ERASE RESUME command. ERASE OPERATIONS An ERASE operation must be used to initialize all bits in an array block to "1s." After BLOCK ERASE confirm is issued, the CSM responds only to an ERASE SUSPEND command until the WSM completes its task. Block erasure inside the memory array sets all bits within the address block to logic 1s. Erase is accom- Table 8 Bus Operations MODE Read (array, status registers, device identification register, or query) Standby Output Disable Reset Write F_RP# VIH F_CE# VIL F_OE# VIL F_WE# VIH ADDRESS DQ0-DQ15 X DOUT VIH VIH VIL VIH VIH VIH X VIL X X X VIH X X X VIL X X X X High-Z High-Z High-Z DIN 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Table 9 Status Register Bit Definition WSMS 7 ESS 6 ES 5 PS 4 VPPS 3 PSS 2 BLS 1 R 0 STATUS BIT # STATUS REGISTER BIT SR7 DESCRIPTION WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word 1 = Ready program or block erase completion, before checking 0 = Busy program or erase status bits. ERASE SUSPEND STATUS (ESS) 1 = BLOCK ERASE Suspended 0 = BLOCK ERASE in Progress/Completed ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful BLOCK ERASE PROGRAM STATUS (PS) 1 = Error in PROGRAM 0 = Successful PROGRAM VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP = OK When ERASE SUSPEND is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set to "1" until an ERASE RESUME command is issued. When this bit is set to "1," WSM has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to "1," WSM has attempted but failed to program a word. The VPP status bit does not provide continuous indication of the VPP level. The WSM interrogates the VPP level only after the program or erase command sequences have been entered and informs the system if VPP has not been switched on. The VPP level is also checked before the PROGRAM/ERASE operation is verified by the WSM. The MT28C3212P2NFL device allows PROGRAM or ERASE at 0V, in which case SR3 is held at "0." When PROGRAM SUSPEND is issued, WSM halts execution and sets both WSM and PSS bits to "1." PSS bit remains set to "1" until a PROGRAM RESUME command is issued. If a PROGRAM or ERASE operation is attempted to one of the locked blocks, this is set by the WSM. The operation specified is aborted, and the device is returned to read status mode. This bit is reserved for future. SR6 SR5 SR4 SR3 SR2 PROGRAM SUSPEND STATUS (PSS) 1 = PROGRAM Suspended 0 = PROGRAM in Progress/Completed BLOCK LOCK STATUS (BLS) 1 = PROGRAM/ERASE Attempted on a Locked Block; Operation Aborted 0 = No Operation to Locked Blocks RESERVED FOR FUTURE ENHANCEMENT SR1 SR0 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Figure 4 Automated Word Programming Flowchart Start BUS OPERATION COMMAND COMMENTS WRITE WRITE PROGRAM SETUP WRITE DATA Data = Addr = Data = Addr = READ 40h or 10h Address of word to be programmed Word to be programmed Address of word to be programmed WRITE Issue PROGRAM SETUP Command and Word Address Issue Word Address and Word Data Status register data; toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy Standby Read Status Register Bits NO NO SR7 = 1? YES Full Status Register Check (optional)1 PROGRAM SUSPEND? PROGRAM SUSPEND Loop Repeat for subsequent words. Write FFh after the last word programming operation to reset the device to read array mode. YES Word Program Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits BUS OPERATION COMMAND COMMENTS Standby Standby Check SR1 1 = Detect locked block Check SR32 1 = Detect VPP low Check SR43 1 = Word program error SR1 = 0? YES NO PROGRAM Attempted on a Locked Block Standby NO SR3 = 0? YES NO SR4 = 0? YES Word Program Passed VPP Range Error Word Program Failed NOTE: 1. Full status register check can be done after each word or after a sequence of words. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation attempts. 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Figure 5 PROGRAM SUSPEND/ PROGRAM RESUME Flowchart Start BUS OPERATION COMMAND COMMENTS WRITE READ PROGRAM SUSPEND Data = B0h Status register data; toggle OE# or CE# to update status register. Check SR7 1 = Ready Check SR2 1 = Suspended READ MEMORY Data = FFh Read data from block other than that being programmed. PROGRAM RESUME Data = D0h Issue PROGRAM SUSPEND Command Standby Standby Read Status Register Bits WRITE READ WRITE NO SR7 = 1? YES NO SR2 = 1? YES Issue READ ARRAY Command PROGRAM Complete Finished Reading ? YES Issue PROGRAM RESUME Command NO PROGRAM Resumed 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Figure 6 BLOCK ERASE Flowchart Start Issue ERASE SETUP Command and Block Address BUS OPERATION COMMAND COMMENTS WRITE WRITE ERASE SETUP ERASE Data = 20h Block Addr = Address within block to be erased Data = D0h Block Addr = Address within block to be erased Status register data; toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy WRITE READ Issue BLOCK ERASE CONFIRM Command and Block Address Standby ERASE SUSPEND Loop NO NO Read Status Register Bits Repeat for subsequent blocks. Write FFh after the last BLOCK ERASE operation to reset the device to read array mode. SR 7 = 1? YES Full Status Register Check (optional)1 ERASE SUSPEND? YES BLOCK ERASE Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits BUS OPERATION COMMAND COMMENTS Standby Standby Standby ERASE Attempted on a Locked Block Check SR1 1 = Detect locked block Check SR32 1 = Detect VPP block Check SR4 and SR5 1 = BLOCK ERASE command error Check SR53 1 = BLOCK ERASE error NO SR1 = 0? YES NO SR3 = 0? YES NO SR5 = 0? YES BLOCK ERASE Passed Standby VPP Range Error BLOCK ERASE Failed NOTE: 1. Full status register check can be done after each block or after a sequence of blocks. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked. 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Figure 7 ERASE SUSPEND/ERASE RESUME Flowchart Start BUS OPERATION COMMAND COMMENTS WRITE READ ERASE SUSPEND Data = B0h Status register data; toggle OE# or CE# to update status register. Check SR7 1 = Ready Check SR6 1 = Suspended READ MEMORY Data = FFh Read data from block other than that being erased. ERASE RESUME Data = D0h Issue ERASE SUSPEND Command Standby Standby Read Status Register Bits WRITE READ NO SR7 = 1? WRITE YES NO SR6 = 1? YES ERASE Complete PROGRAM READ or PROGRAM? READ Issue READ ARRAY Command PROGRAM Loop (Note 1) NO READ or PROGRAM Complete? YES Issue ERASE RESUME Command ERASE Continued2 NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure. 2. See Word Programming Flowchart for complete programming procedure. 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY The Flash memory of the MT28C3212P2FL or MT28C3212P2NFL device provides a flexible locking scheme which allows each block to be individually locked or unlocked with no latency. The device offers two-level protection for the blocks. The first level allows software-only control of block locking (for data which needs to be changed frequently), while the second level requires hardware interaction before locking can be changed (code which does not require frequent updates). Control pins F_WP#, DQ0, and DQ1 define the state of a block; for example, state [001] means F_WP# = 0, DQ0 = 0 and DQ1 = 1. Table 10 defines all of the possible locking states. NOTE: All blocks are software-locked upon completion of the power-up sequence. LOCKED STATE After a power-up sequence completion, or after a reset sequence, all blocks are locked (states [001] or [101]). This means full protection from alteration. Any PROGRAM or ERASE operations attempted on a locked block will return an error on bit SR1 of the status register. The status of a locked block can be changed to unlocked or lock down using the appropriate software commands. Writing the lock command sequence, 60h followed by 01h, can lock an unlocked block. UNLOCKED STATE Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the locked state when the device is reset or powered down. An unlocked block can be locked or locked down using the appropriate software command sequence, 60h followed by D0h. (See Table 5.) LOCKED DOWN STATE Blocks locked down (state [011]) are protected from PROGRAM and ERASE operations, but their protection status cannot be changed using software commands It is possible for the device to read from one bank while erasing/writing to another bank. Once a bank enters the WRITE/ERASE operation, the other bank automatically enters read array mode. For example, during a READ CONCURRENCY operation, if a PROGRAM/ERASE command is issued in bank a, then bank a changes to the read status mode and bank b defaults to the read array mode. The device reads from bank b if the latched address resides in bank b (see Figure 8). Similarly, if a PROGRAM/ERASE command is issued in bank b, then bank b changes to read status mode and bank a defaults to read array mode. When returning to bank a, the device reads program/erase status if the latched address resides in bank a. A correct bank address must be specified to read status register after returning from concurrent read in the other bank. When reading the CFI area, or the chip protection register, the possible concurrent operations are reported in Figures 9a and 9b. Figure 8 READ-While-WRITE Concurrency Bank a 1 - Erasing/writing to bank a 2 - Erasing in bank a can be suspended, and a WRITE to another block in bank a can be initiated. 3 - After the WRITE in that block is complete, an ERASE can be resumed by writing an ERASE RESUME command. 1 - Reading bank a Bank b 1 - Reading from bank b 1 - Erasing/writing to bank b 2 - Erasing in bank b can be suspended, and a WRITE to another block in bank b can be initiated. 3 - After the WRITE in that block is complete, an ERASE can be resumed by writing an ERASE RESUME command. Figure 9a Top Boot Block Device BANK a Reading the CFI or Chip Protection Register READ WRITE ERASE Not Supported Not Supported BANK b Not Supported Not Supported Figure 9b Bottom Boot Block Device BANK a Reading the CFI or Chip Protection Register READ WRITE ERASE Not Supported Not Supported BANK b Supported Supported 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH READ-WHILE-WRITE/ERASE CONCURRENCY BLOCK LOCKING 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Table 10 Block Locking State Transition F_WP# 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 NAME Unlocked Locked (Default) Lock Down Unlocked Locked Lock Down Disabled Lock Down Disabled ERASE/PROGRAM ALLOWED Yes No No Yes No Yes No LOCK To [001] - - To [101] - To [111] - UNLOCK - To [000] - - To [100] - To [110] LOCK DOWN To [011] To [011] - To [111] To [111] To [111] - alone. A locked or unlocked block can be locked down by writing the lock down command sequence, 60h followed by 2Fh. Locked down blocks revert to the locked state when the device is reset or powered down. The LOCK DOWN function is dependent on the F_WP# input pin. When F_WP# = 0, blocks in lock down [011] are protected from program, erase, and lock status changes. When F_WP# = 1, the LOCK DOWN function is disabled ([111]) and locked down blocks can be individually unlocked by a software command to the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and unlocked [110], as desired, as long as F_WP# remains HIGH. When F_WP# goes LOW, blocks that were previously locked down return to the lock down state [011] regard- less of any changes made while F_WP# was HIGH. Device reset or power-down resets all locks, including those in lock down, to the locked state (see Table 10). READING A BLOCK'S LOCK STATUS The lock status of every block can be read in the read device identification mode. To enter this mode, write 90h to the bank containing address 00h. Subsequent READs at block address +00002 will output the lock status of that block. The lowest two output pins, DQ0 and DQ1, represent the lock status. DQ0 indicates the block lock/unlock status and is set by the LOCK command and cleared by the UNLOCK command. It is also automatically set when entering lock down. DQ1 indicates lock down status and is set by the LOCK Table 11 Chip Protection Configuration Addressing1 ITEM Manufacturer Code (x16) Device Code Top boot configuration Bottom boot configuration 2 ADDRESS 00000h 00001h DATA 002Ch 44A2h 44A3h * * Block Lock Configuration is unlocked * Block is locked Block * Block is locked down * XX002h Lock DQ0 = 0 DQ0 = 1 DQ1 = 1 PR Lock Factory Data User Data Chip Protection Register Lock Chip Protection Register 1 Chip Protection Register 2 80h 81h-84h 85h-88h NOTE: 1. Other locations within the configuration address space are reserved by Micron for future use. 2. "XX" specifies the block address of lock configuration. 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY DOWN command. It can only be cleared by reset or power-down, not by software. Table 10 shows the block locking state transition scheme. The READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. LOCKING OPERATIONS DURING ERASE SUSPEND Changes to block lock status can be performed during an ERASE SUSPEND by using the standard locking command sequences to unlock, lock, or lock down. This is useful in the case when another block needs to be updated while an ERASE operation is in progress. To change block locking during an ERASE operation, first write the ERASE SUSPEND command (B0h), then check the status register until it indicates that the ERASE operation has been suspended. Next, write the desired lock command sequence to block lock, and the lock status will be changed. After completing any desired LOCK, READ, or PROGRAM operations, resume the ERASE operation with the ERASE RESUME command (D0h). If a block is locked or locked down during an ERASE SUSPEND on the same block, the locking status bits are changed immediately. When the ERASE is resumed, the ERASE operation completes. A locking operation cannot be performed during a PROGRAM SUSPEND. STATUS REGISTER ERROR CHECKING Using nested locking or program command sequences during ERASE SUSPEND can introduce ambiguity into status register results. Following protection configuration setup (60h), an invalid command produces a lock command error (SR4 and SR5 are set to "1") in the status register. If a lock command error occurs during an ERASE SUSPEND, SR4 and SR5 are set to "1" and remain at "1" after the ERASE SUSPEND command is issued. When the ERASE is complete, any possible error during the ERASE cannot be detected via the status register because of the previous locking command error. A similar situation happens if an error occurs during a program operation error nested within an ERASE SUSPEND. The 128-bit security area is divided into two 64-bit segments. The first 64 bits are programmed at the manufacturing site with a unique 64-bit number. The other segment is left blank for customers to program as desired. (See Figure 10). READING THE CHIP PROTECTION REGISTER The chip protection register is read in the device identification mode. To enter this mode, load the 90h command to the bank containing address 00h. Once in this mode, READ cycles from addresses shown in Table 11 retrieve the specified information. To return to the read array mode, write the READ ARRAY command (FFh). The read array command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. PAGE READ MODE The initial portion of the page mode cycle is the same as the asynchronous access cycle. Holding CE# LOW and toggling addresses A0-A1 allows random access of other words in the page. The page size can be customized at the factory to four or eight words as required; but if no specification is made, the normal size is four words. ASYNCHRONOUS READ CYCLE When accessing addresses in a random order or when switching between pages, the access time is given by tAA. When F_CE# and F_OE# are LOW, the data is placed on the data bus and the processor can read the data. Figure 10 Protection Register Memory Map 88h 85h 84h 4 Words User-Programmed 4 Words Factory-Programmed CHIP PROTECTION REGISTER A 128-bit protection register can be used to fullfill the security considerations in the system (preventing device substitution). 81h 80h PR Lock 0 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY STANDBY MODE Icc supply current is reduced by applying a logic HIGH level on F_CE# and F_RP# to enter the standby mode. In the standby mode, the outputs are placed in High-Z. Applying a CMOS logic HIGH level on F_CE# and F_RP# reduces the current to ICC2 (MAX). If the device is deselected during an ERASE operation or during programming, the device continues to draw current until the operation is complete. During WRITE and ERASE operations, the WSM monitors the VPP voltage level. WRITE/ERASE operations are allowed only when VPP is within the ranges specified in Table 12. When VCC is below VLKO or VPP is below VPPLK, any WRITE/ERASE operation is prevented. DEVICE RESET To correctly reset the device, the RST# signal must be asserted (RST# = VIL) for a minimum of tRP. After reset, the device can be accessed for a READ operation with a delayed access time of tRWH from the rising edge of RST#. The circuitry used for generating the RST# signal needs to be common with the rest of the system reset to ensure that correct system initialization occurs. Please refer to the timing diagram for further details. AUTOMATIC POWER SAVE MODE (APS) Substantial power savings are realized during periods when the Flash array is not being read and the device is in the active mode. During this time the device switches to the automatic power save (APS) mode. When the device switches to this mode, ICC is reduced to ICC2. The low level of power is maintained until another operation is initiated. In this mode, the I/O pins retain the data from the last memory address read until a new address is read. This mode is entered automatically if no address or control pins toggle. POWER-UP SEQUENCE The following power-up sequence must be observed to properly initialize the device: * RST# must be at VIL. * Power on VCC/VCCQ (VCC VCCQ at all times). * Wait 2S after VCC reaches VCC (MIN). * Take RST# from VIL to VIH. * The RST# transition from VIL to VIH must be less than 10S. VPP/VCC PROGRAM AND ERASE VOLTAGES The MT28C3212P2FL Flash memory provides insystem programming and erase with VPP in the 0.9V- 2.2V range (VPP1). In addition to the flexible block locking, the VPP programming voltage can be held LOW for absolute hardware write protection of all blocks in the Flash device. When VPP is below VPPLK, any PROGRAM or ERASE operation results in an error, prompting the corresponding status register bit (SR3) to be set. The MT28C3212P2NFL Flash memory provides insystem programming and erase with VPP in the 0.0V- 2.2V range (VPP1). VPP at 12V 5% (VPP2) is supported for a maximum of 100 cycles and 10 cumulative hours. The device can withstand 100,000 WRITE/ERASE operations when VPP = VCC. Table 12 VPP Ranges (V) DEVICE MT28C3212P2FL MT28C3212P2NFL IN-SYSTEM MIN MAX 0.9 2.2 0.0 2.2 IN-FACTORY MIN MAX 11.4 12.6 11.4 12.6 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS* Voltage to Any Pin Except VCC and VPP with Respect to VSS ............................ -0.5V to +2.45V VPP Voltage (for BLOCK ERASE and PROGRAM with Respect to VSS) ....................... -0.5V to +13.5V** VCC and VCCQ Supply Voltage with Respect to VSS ............................ -0.3V to +2.45V Output Short Circuit Current ............................... 100mA Operating Temperature Range .............. -40oC to +85oC Storage Temperature Range ................. -55oC to +125oC Soldering Cycle ........................................... 260 oC for 10s *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum DC voltage on VPP may overshoot to +13.5V for periods <20ns. RECOMMENDED OPERATING CONDITIONS PARAMETER Operating temperature VCC supply voltage I/O supply voltage (VCC = 1.65V-1.95V) I/O supply voltage (VCC = 1.80V-2.20V) VPP voltage (MT28C3212P2FL only) VPP voltage (MT28C3212P2NFL only) VPP in-factory programming voltage Data retention supply voltage Block erase cycling SYMBOL tA MIN -40 1.65 1.65 1.80 0.9 0.0 11.4 1.0 - MAX +85 2.2 1.95 2.20 2.2 2.2 12.6 - 100,000 UNITS oC NOTES F_VCC, S_VCC VCCQ VCCQ VPP1 VPP1 VPP2 S_VDR V V V V V V V Cycles 2 1 1 NOTE: 1. Use only one of the two I/O supply voltage ranges, 1.65V-1.95V or 1.80V-2.20V. 2. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours. Figure 11 Output Load Circuit VCC 14.5K I/O 14.5K VSS 30pF 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY COMBINED DC CHARACTERISTICS1 VCC = 1.65V-1.95V or 1.80V-2.20V VCCQ = 1.65V-1.95V or 1.80V-2.20V DESCRIPTION Input low voltage Input high voltage Output low voltage IOL = 100A Output high voltage IOH = 100A VPP lock out voltage VPP during PROGRAM/ERASE operations (MT28C3212P2FL only) VPP during PROGRAM/ERASE operations (MT28C3212P2NFL only) VCC PROGRAM/ERASE lock voltage Input leakage current Output leakage current F_VCC asynchronous read current at 95ns F_VCC page mode read current at 35ns F_VCC plus S_VCC standby current F_VCC program current F_VCC erase current F_VCC/S_VCC erase suspend current F_VCC/S_VCC program suspend current Read-while-write current S_VCC read/write operating supply current - page access mode VIN = VIH or VIL chip enabled, IOL = 0 CONDITIONS SYMBOL VIL VIH VOL VOH VPPLK VPP1 VPP2 VPP1 VPP2 VLKO IL IOZ ICC1 ICC2 ICC3 ICC4+IPP3 ICC5+IPP4 ICC6 ICC7 ICC8 ICC9 MIN -0.4 VCCQ 0.4V - VCCQ 0.1V - 0.9 11.4 0.0 11.4 1.0 - - - - - - - - - - - TYP - - - - - - - - - - - - - - 25 - - - - - 12 MAX 0.4 VCCQ + 0.3V 0.10 - 0.4 2.2 12.6 2.2 12.6 - 1 1 15 5 60 55 65 60 60 80 25 UNITS NOTES V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA 3 2 2 NOTE: 1. All currents are in RMS unless otherwise noted. 2. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours. 3. Operating current is a linear function of operating frequency and voltage. Operating current can be calculated using the formula shown with operating frequency (f) expressed in MHz and operating voltage (V) in volts. Example: When operating at 2 MHz at 2V, the device will draw a typical active current of 0.8*2* = 3.2mA in the page access mode. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. (continued on the next page) 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY COMBINED DC CHARACTERISTICS1 (continued) VCC = 1.65V-1.95V or 1.80V-2.20V VCCQ = 1.65V-1.95V or 1.80V-2.20V DESCRIPTION S_VCC read/write operating supply current - word access mode VPP read current VPP standby current VPP erase suspend current VPP program suspend current CONDITIONS VIN = VIH or VIL chip enabled, IOL = 0 VPP VCC VPP VCC VPP VCC VPP VCC VPP = VPP1 VPP = VPP2 VPP = VPP1 VPP = VPP2 IPP6 IPP5 IPP2 SYMBOL ICC10 MIN - TYP 3 MAX 8 UNITS NOTES mA 3 IPP1 - - - - - - - - - - - - - - - - 1 200 1 200 1 200 1 200 mA mA mA mA mA mA mA mA NOTE: 1. All currents are in RMS unless otherwise noted. 2. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours. 3. Operating current is a linear function of operating frequency and voltage. Operating current can be calculated using the formula shown with operating frequency (f) expressed in MHz and operating voltage (V) in volts. Example: When operating at 2 MHz at 2V, the device will draw a typical active current of 0.8*2* = 3.2mA in the page access mode. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH READ CYCLE TIMING REQUIREMENT VCC = 1.65V-1.95V -10 VCC = 1.65V-1.95V MIN MAX 100 100 35 30 200 125 25 0 100 -11 VCC = 1.65V-1.95V MIN MAX 110 110 45 30 200 125 25 0 110 PARAMETER Address to output delay CE# LOW to output delay Page address access OE# LOW to output delay F_RP# HIGH to output delay F_RP# LOW pulse width CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# change READ cycle time SYMBOL tAA tACE tAPA tAOE tRWH tRP tOD tOH tRC UNITS ns ns ns ns ns ns ns ns ns FLASH READ CYCLE TIMING REQUIREMENT VCC = 1.80V-2.20V -10 VCC = 1.80V-2.20V MIN MAX 95 95 35 30 150 100 25 0 95 -11 VCC = 1.80V-2.20V MIN MAX 100 100 45 30 150 100 25 0 100 PARAMETER Address to output delay CE# LOW to output delay Page address access OE# LOW to output delay F_RP# HIGH to output delay F_RP# LOW pulse width CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# change READ cycle time SYMBOL tAA tACE tAPA tAOE tRWH tRP tOD tOH tRC UNITS ns ns ns ns ns ns ns ns ns 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH WRITE CYCLE TIMING REQUIREMENTS -10/-11 VCC = 1.65V-1.95V or 1.80V-2.20V PARAMETER Reset HIGH recovery to WE# going LOW CE# setup to WE# going LOW Write pulse width Data setup to WE# going HIGH Address setup to WE# going HIGH CE# hold from WE# HIGH Data hold from WE# HIGH Address hold from WE# HIGH Write pulse width HIGH WP# setup to WE# going HIGH VPP setup to WE# going HIGH Write recovery before READ WP# hold from valid SRD VPP hold from valid SRD WE# HIGH to data valid SYMBOL tRS tCS tWP tDS tAS tCH tDH tAH tWPH tRHS tVPS tWOS tRHH tVPH tWB MIN 150 0 50 50 50 0 0 9 30 200 200 50 0 0 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tAA+50 FLASH ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS -10/-11 VCC = 1.65V-1.95V or 1.80V-2.20V PARAMETER 4KW parameter block program time 32KW parameter block program time Word program time 4KW parameter block erase time 32KW parameter block erase time Program suspend latency Erase suspend latency TYP 0.1 0.8 8 1 1.5 5 5 MAX 0.3 2.4 185 4 5 10 20 UNITS s s s s s s s 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY TWO-CYCLE PROGRAMMING/ERASE OPERATION A0-A20 VIH VALID ADDRESS VIL VIH CE# VIL tCS tCH tWOS VALID ADDRESS tAS tAH VALID ADDRESS VIH OE# VIL VIH WE# VIL VOH DQ0-DQ15 VOL High-Z tRS tDH tRHS tWP tWB tWPH CMD CMD/ DATA tDS STATUS VIH RP# VIL VIH WP# VIL tRHH tVPS tVPPH VIPPH VIPPLK VPP VIL UNDEFINED WRITE TIMING PARAMETERS -10/-11 VCC = 1.65V-1.95V or 1.80V-2.20V SYMBOL tRS tCS tWP tDS tAS tCH tDH -10/-11 VCC = 1.65V-1.95V or 1.80V-2.20V UNITS ns ns ns ns ns ns ns SYMBOL tAH tRHS tVPS tWOS tRHH tVPH tWB MIN 150 0 50 50 50 0 0 MAX MIN 9 200 200 50 0 0 MAX UNITS ns ns ns ns ns ns tAA+50 ns NOTE: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle. 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY SINGLE ASYNCHRONOUS READ OPERATION A0-A20 VIH VALID ADDRESS VIL tRC tAA tOD VIH CE# VIL tACE VIH OE# VIL tOH VIH WE# VIL VOH DQ0-DQ15 VOL tAOE High-Z tRWH VALID OUTPUT RP# VIH VIL UNDEFINED READ TIMING PARAMETERS (VCC = 1.65V-1.95V) -10 -11 VCC = 1.65V-1.95V VCC = 1.65V-1.95V SYMBOL tAA tACE tAOE tRWH tOD tOH tRC READ TIMING PARAMETERS (VCC = 1.80V-2.20V) -10 -11 VCC = 1.80V-2.20V VCC = 1.80V-2.20V UNITS ns ns ns ns ns ns ns SYMBOL tAA tACE tAOE tRWH tOD tOH tRC MIN MAX 100 100 30 200 25 MIN MAX 110 110 30 200 25 MIN MAX 95 95 30 150 25 MIN MAX 100 100 30 150 25 UNITS ns ns ns ns ns ns ns 0 100 0 110 0 95 0 100 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY ASYNCHRONOUS PAGE MODE READ OPERATION A2-A20 VIH VALID ADDRESS VIL VIH VALID ADDRESS VIL tAA tOD A0-A1 VALID ADDRESS VALID ADDRESS VALID ADDRESS VIH F_CE# VIL tACE VIH F_OE# VIL VIH F_WE# VIL tAOE tAPA tOH VOH DQ0-DQ15 VOL High-Z tRMH VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VIH F_RP# VIL UNDEFINED READ TIMING PARAMETERS (VCC = 1.65V-1.95V) -10 SYMBOL tAA tACE tAPA tAOE tRWH tOD tOH READ TIMING PARAMETERS (VCC = 1.80V-2.20V) -11 SYMBOL tAA tACE tAPA tAOE tRWH tOD tOH -10 -11 VCC = 1.65V-1.95V VCC = 1.65V-1.95V MIN MAX MIN MAX UNITS 100 110 ns 100 35 30 200 25 0 0 110 45 30 200 25 ns ns ns ns ns ns VCC = 1.80V-2.20V VCC = 1.80V-2.20V MIN MAX MIN MAX UNITS 95 100 ns 95 35 30 150 25 0 0 100 45 30 150 25 ns ns ns ns ns ns 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY RESET OPERATION VIH VIL F_RST# VIH VIL tRP F_CE# F_OE# VIH VIL DQ0-DQ15 VOH VOL tRWH READ TIMING PARAMETERS (VCC = 1.65V-1.95V) -10 -11 VCC = 1.65V-1.95V VCC = 1.65V-1.95V MIN MAX MIN MAX UNITS 200 200 ns 125 125 ns READ TIMING PARAMETERS (VCC = 1.80V-2.20V) -10 -11 VCC = 1.80V-2.20V VCC = 1.80V-2.20V MIN MAX MIN MAX UNITS 150 150 ns 100 100 ns SYMBOL tRWH tRP SYMBOL tRWH tRP 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Table 15 CFI OFFSET 00 01 02-0F 10, 11 12 13, 14 15, 16 17, 18 19, 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A, 2B 2C 2D, 2E 2F, 30 31, 32 33, 34 35, 36 DATA 2Ch A2h A3h reserved 0051,0052 0059 0003, 0000 0039, 0000 0000, 0000 0000, 0000 0017 0022 00B4 00C6 0003 0000 0009 0000 000C 0000 0003 0000 0016 0001 0000 0000, 0000 0003 0037, 0000 0007, 0000 0000, 0001 0020, 0000 0006, 0000 0000, 0001 0007, 0000 0037, 0000 Manufacturer Code Top Boot Block Device Code Bottom Boot Block Device Code Reserved "QR" "Y" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set Address for OEM Extended Table VCC MIN for Erase/Write; Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD VCC MAX for Erase/Write; Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD VPP MIN for Erase/Write; Bit7-Bit4 Volts in Hex; Bit3-Bit0 100mV in BCD VPP MAX for Erase/Write; Bit7-Bit4 Volts in Hex; Bit3-Bit0 100mV in BCD Typical timeout for single byte/word program, 2n s, 0000 = not supported Typical timeout for maximum size multiple byte/word program, 2n s, 0000 = not supported Typical timeout for individual block erase, 2n ms, 0000 = not supported Typical timeout for full chip erase, 2n ms, 0000 = not supported Maximum timeout for single byte/word program, 2n s, 0000 = not supported Maximum timeout for maximum size multiple byte/word program, 2n s, 0000 = not supported Maximum timeout for individual block erase, 2n ms, 0000 = not supported Maximum timeout for full chip erase, 2n ms, 0000 = not supported Device size, 2n bytes Bus Interface x8 = 0, x16 = 1, x8/x16 = 2 Flash device interface description 0000 = async Maximum number of bytes in multi-byte program or page, 2n Number of erase block regions within device (4K words and 32K words) Top boot block device erase block region information 1, 8 blocks ... Bottom boot block device erase block region information 1, 8 blocks ... Top boot block device ...of 8KB Bottom boot block device ...of 8KB 7 blocks of ... ......64KB Top boot block device 56 blocks of Bottom boot block device 56 blocks of (continued on the next page) 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 DESCRIPTION 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH Table 15 CFI (continued) OFFSET 37, 38 39, 3A 3B 3C 3D 3E 3F 40 41 DATA 0020, 0000 0000, 0001 0050, 0052 0049 0030 0031 00E6 0002 0000 0000 Top boot block device......64KB Bottom boot block device......64KB "PR" "I" Major version number, ASCII Minor Version Number, ASCII Optional Feature and Command Support Bit 0 Chip erase supported no = 0 Bit 1 Suspend erase supported = yes = 1 Bit 2 Suspend program supported = yes = 1 Bit 3 Chip lock/unlock supported = no = 0 Bit 4 Queued erase supported = no = 0 Bit 5 Instant individual block locking supported = yes = 1 Bit 6 Protection bits supported = yes = 1 Bit 7 Page mode read supported = yes = 1 Bit 8 Synchronous read supported = yes = 1 Bit 9 Simultaneous operation supported = yes = 1 Program supported after erase suspend = yes Bit 0 Block Lock Status active = yes; Bit 1 Block Lock Down active = yes VCC supply optimum; Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD VPP supply optimum; Bit7-Bit4 Volts in Hex; Bit3-Bit0 100mV in BCD Number of protection register fields in JEDEC ID space Lock bytes LOW address, lock bytes HIGH address 2n factory programmed bytes, 2n user programmable bytes Background Operation 0000 = Not used 0001 = 4% block split 0002 = 12% block split 0003 = 25% block split 0004 = 50% block split Burst 0000 00x1 00x2 00x3 001x 002x 004x Page 0000 0001 0002 0003 0004 Mode Type = No burst mode = 4 words max = 8 words max = 16 words max = Linear burst, and/or = Interleaved burst, and/or = Continuous burst Mode Type = No page mode = 4-word page = 8-word page = 16-word page = 32-word page DESCRIPTION 42 43, 44 45 46 47 48, 49 4A, 4B 4C 0001 0003, 0000 0018 00C0 0001 0080, 0000 0003, 0003 0002 4D 0000 4E 0002 4F 0002 SRAM density, 2Mb (128K x 16) 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY SRAM OPERATING MODES SRAM READ ARRAY The operational state of the SRAM is determined by S_CE1#, S_CE2, S_WE#, S_OE#, S_UB#, and S_LB#, as indicated in the Truth Table. To perform an SRAM READ operation, S_CE1#, and S_OE#, must be at VIL, and S_CE2 and S_WE# must be at VIH. When in this state, S_UB# and S_LB# control whether the lower byte is read (S_UB# VIH, S_LB# VIL), the upper byte is read (S_UB# VIL, S_LB# VIH), both upper and lower bytes are read (S_UB# VIL, S_LB# VIL), or neither are read (S_UB# VIH, S_LB# VIH) and the device is in a standby state. While performing an SRAM READ operation, current consumption may be reduced by reading within a 16-word page. This is done by holding S_CE1# and S_OE# at VIL, S_WE# and S_CE2 at VIH, and toggling addresses A0-A3. S_UB# and S_LB# control the data width as described above. SRAM WRITE ARRAY In order to perform an SRAM WRITE operation, S_CE1# and S_WE# must be at VIL, and S_CE2 and S_OE# must be at VIH. When in this state, S_UB# and S_LB# control whether the lower byte is written (S_UB# VIH, S_LB# VIL), the upper byte is written (S_UB# VIL, S_LB# VIH), both upper and lower bytes are written (S_UB# VIL, S_LB# VIL), or neither are written (S_UB# VIH, S_LB# VIH) and the device is in a standby state. SRAM FUNCTIONAL BLOCK DIAGRAM WORD ADDRESS DECODE LOGIC A0-A3 A4-A16 PAGE ADDRESS DECODE LOGIC 8K-PAGE x16 WORD x16 BIT RAM ARRAY WORD MUX INPUT/ OUTPUT MUX AND BUFFERS DQ0-DQ7 DQ8-DQ15 S_CE1# S_CE2 S_WE# S_OE# S_UB# S_LB# CONTROL LOGIC 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. SRAM 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY TIMING TEST CONDITIONS Input pulse levels .................... 0.1V VCC to 0.9V VCC Input rise and fall times .................................... 5ns Input timing reference levels ......................... 0.5V Output timing reference levels ..................... 0.5V Operating Temperature ............... -40oC to +85oC SRAM READ CYCLE TIMING -10/-11 VCC = 1.65V-1.95V VCC = 1.80V-2.20V SYMBOL MIN MAX MIN MAX t RC 100 85 t AA 100 85 t CO 100 85 t OE 35 35 tLB, tUB 100 85 t LZ 0 0 t OLZ 0 0 tLBZ, tUBZ 0 0 t HZ 0 15 0 15 t OHZ 0 15 0 15 tLBHZ, tUBHZ 0 15 0 15 t OH 5 5 DESCRIPTION Read cycle time Address access time Chip enable to valid output Output enable to valid output Byte select to valid output Chip enable to Low-Z output Output enable to Low-Z output Byte select to Low-Z output Chip enable to High-Z output Output disable to High-Z output Byte select disable to High-Z output Output hold from address change UNITS ns ns ns ns ns ns ns ns ns ns ns ns SRAM WRITE CYCLE TIMING -10/-11 VCC = 1.65V-1.95V VCC = 1.80V-2.20V MIN MAX MIN MAX 100 85 100 85 100 85 100 85 0 0 50 50 0 0 0 15 0 15 50 50 0 0 0 0 DESCRIPTION Write cycle time Chip enable to end of write Address valid to end of write Byte select to end of write Address setup time Write pulse width Write recovery time Write to High-Z output Data to write time overlap Data hold from write time End write to Low-Z output SYMBOL t WC t CW t AW tLBW, tUBW t AS t WP t WR t WHZ t DW t DH t OW UNITS ns ns ns ns ns ns ns ns ns ns ns 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. SRAM 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY READ CYCLE 1 (S_CE1# = S_OE# = VIL; S_CE2, S_WE# = VIH) tRC ADDRESS tOH DATA-OUT PREVIOUS DATA VALID DATA VALID READ CYCLE 2 (S_WE# = VIH) tRC ADDRESS tAA tHZ (1, 2) S_CE1# tCO S_CE2 tLZ(2) tOE tOHZ (1) S_OE# tOLZ tLB, tUB S_LB#, S_UB# tLBLZ, tUBLZ tLBHZ, tUBHZ DATA VALID DATA-OUT High-Z DON'T CARE READ TIMING PARAMETERS -10/-11 VCC = 1.65V-1.95V VCC = 1.80V-2.20V SYMBOL tRC tAA tCO tOE tLB, tUB tLZ -10/-11 VCC = 1.65V-1.95V VCC = 1.80V-2.20V UNITS ns ns ns ns ns ns SYMBOL tOLZ tHZ tOHZ tLBHZ, tUBHZ tOH MIN MAX 100 100 100 35 100 MIN MAX 85 85 85 35 85 MIN 0 0 0 0 5 MAX 15 15 15 MIN 0 0 0 0 5 MAX 15 15 15 UNITS ns ns ns ns ns 0 0 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. SRAM tAA 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY WRITE CYCLE (S_WE# CONTROL) tWC ADDRESS tAW tWR S_CE1# tCW S_CE2 tLBW, tUBW S_LB#, S_UB# tAS tWP S_WE# tDW tDH DATA-IN High-Z tWHZ DATA VALID tOW DATA-OUT High-Z DON'T CARE WRITE TIMING PARAMETERS -10/-11 VCC = 1.65V-1.95V VCC = 1.80V-2.20V MIN MAX MIN MAX 100 85 100 100 100 0 50 0 50 85 85 85 -10/-11 VCC = 1.65V-1.95V VCC = 1.80V-2.20V MIN MAX MIN MAX 0 0 0 50 0 0 15 0 50 0 0 15 SYMBOL tWC tCW tAW tLBW, tUBW tAS tWP UNITS ns ns ns ns ns ns SYMBOL tWR tWHZ tDW tDH tOW UNITS ns ns ns ns ns 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. SRAM 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY WRITE CYCLE 2 (S_CE1# CONTROL) tWC ADDRESS tCW S_CE1# tAS tLBW, tUBW S_LB#, S_UB# tWP S_WE# tDW tDH DATA-IN tLZ tWHZ DATA VALID DATA-OUT High-Z DON'T CARE WRITE TIMING PARAMETERS -10/-11 VCC = 1.65V-1.95V VCC = 1.80V-2.20V MIN MAX MIN MAX 100 85 100 100 100 0 50 0 50 85 85 85 -10/-11 VCC = 1.65V-1.95V VCC = 1.80V-2.20V MIN MAX MIN MAX 0 0 0 50 0 0 15 0 50 0 0 15 SYMBOL tWC tCW tAW tLBW, tUBW tAS tWP UNITS ns ns ns ns ns ns SYMBOL tWR tWHZ tDW tDH tOW UNITS ns ns ns ns ns 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. SRAM tAW tWR 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY 66-BALL FBGA 1.05 0.075 SEATING PLANE 0.10 C C SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 36% Pb, 2%Ag SOLDER BALL PAD: O .27mm SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC BALL A1 BALL #1 ID BALL A1 8.80 66X O 0.35 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS O 0.33 0.80 (TYP) BALL A12 0.80 (TYP) 2.80 0.05 5.60 C L 8.00 0.10 4.00 0.05 C L 4.40 0.05 6.00 0.05 1.40 MAX 12.00 0.10 NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side. DATA SHEET DESIGNATION This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc. 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY REVISION HISTORY Rev. 2, Pub. 4/02 ................................................................................................................................................................ 4/02 * Updated the chip protection mode and register information. * Updated the block locking information. * Removed the tCBPH parameter. Rev. 2, Pub. 6/01 ................................................................................................................................................................ 6/01 * Data sheet designation change (removed "Advance") Initial published release, Rev. 1, Advance ................................................................................................................... 5/01 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 - Rev. 2, Pub. 4/02 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. |
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